enum Arch [src]

Fields

amdgcn
arc
arm
armeb
thumb
thumbeb
aarch64
aarch64_be
avr
bpfel
bpfeb
csky
hexagon
kalimba
lanai
loongarch32
loongarch64
m68k
mips
mipsel
mips64
mips64el
msp430
nvptx
nvptx64
powerpc
powerpcle
powerpc64
powerpc64le
propeller
riscv32
riscv64
s390x
sparc
sparc64
spirv
spirv32
spirv64
wasm32
wasm64
x86
x86_64
xcore
xtensa
Members

allCpuModels (Function)
allFeaturesList (Function)
endian (Function)
fromCallingConvention (Function)
genericName (Function)
isAARCH64 (Function)
isArm (Function)
isBpf (Function)
isLoongArch (Function)
isMIPS (Function)
isMIPS32 (Function)
isMIPS64 (Function)
isNvptx (Function)
isPowerPC (Function)
isPowerPC32 (Function)
isPowerPC64 (Function)
isRISCV (Function)
isSPARC (Function)
isSpirV (Function)
isThumb (Function)
isWasm (Function)
isX86 (Function)
parseCpuModel (Function)
plan9Ext (Function)
Source

  pub const Arch = enum {
    amdgcn,
    arc,
    arm,
    armeb,
    thumb,
    thumbeb,
    aarch64,
    aarch64_be,
    avr,
    bpfel,
    bpfeb,
    csky,
    hexagon,
    kalimba,
    lanai,
    loongarch32,
    loongarch64,
    m68k,
    mips,
    mipsel,
    mips64,
    mips64el,
    msp430,
    nvptx,
    nvptx64,
    powerpc,
    powerpcle,
    powerpc64,
    powerpc64le,
    propeller,
    riscv32,
    riscv64,
    s390x,
    sparc,
    sparc64,
    spirv,
    spirv32,
    spirv64,
    ve,
    wasm32,
    wasm64,
    x86,
    x86_64,
    xcore,
    xtensa,

    // LLVM tags deliberately omitted:
    // - aarch64_32
    // - amdil
    // - amdil64
    // - dxil
    // - le32
    // - le64
    // - r600
    // - hsail
    // - hsail64
    // - renderscript32
    // - renderscript64
    // - shave
    // - sparcel
    // - spir
    // - spir64
    // - tce
    // - tcele

    pub inline fn isX86(arch: Arch) bool {
        return switch (arch) {
            .x86, .x86_64 => true,
            else => false,
        };
    }

    /// Note that this includes Thumb.
    pub inline fn isArm(arch: Arch) bool {
        return switch (arch) {
            .arm, .armeb => true,
            else => arch.isThumb(),
        };
    }

    pub inline fn isThumb(arch: Arch) bool {
        return switch (arch) {
            .thumb, .thumbeb => true,
            else => false,
        };
    }

    pub inline fn isAARCH64(arch: Arch) bool {
        return switch (arch) {
            .aarch64, .aarch64_be => true,
            else => false,
        };
    }

    pub inline fn isWasm(arch: Arch) bool {
        return switch (arch) {
            .wasm32, .wasm64 => true,
            else => false,
        };
    }

    pub inline fn isLoongArch(arch: Arch) bool {
        return switch (arch) {
            .loongarch32, .loongarch64 => true,
            else => false,
        };
    }

    pub inline fn isRISCV(arch: Arch) bool {
        return switch (arch) {
            .riscv32, .riscv64 => true,
            else => false,
        };
    }

    pub inline fn isMIPS(arch: Arch) bool {
        return arch.isMIPS32() or arch.isMIPS64();
    }

    pub inline fn isMIPS32(arch: Arch) bool {
        return switch (arch) {
            .mips, .mipsel => true,
            else => false,
        };
    }

    pub inline fn isMIPS64(arch: Arch) bool {
        return switch (arch) {
            .mips64, .mips64el => true,
            else => false,
        };
    }

    pub inline fn isPowerPC(arch: Arch) bool {
        return arch.isPowerPC32() or arch.isPowerPC64();
    }

    pub inline fn isPowerPC32(arch: Arch) bool {
        return switch (arch) {
            .powerpc, .powerpcle => true,
            else => false,
        };
    }

    pub inline fn isPowerPC64(arch: Arch) bool {
        return switch (arch) {
            .powerpc64, .powerpc64le => true,
            else => false,
        };
    }

    pub inline fn isSPARC(arch: Arch) bool {
        return switch (arch) {
            .sparc, .sparc64 => true,
            else => false,
        };
    }

    pub inline fn isSpirV(arch: Arch) bool {
        return switch (arch) {
            .spirv, .spirv32, .spirv64 => true,
            else => false,
        };
    }

    pub inline fn isBpf(arch: Arch) bool {
        return switch (arch) {
            .bpfel, .bpfeb => true,
            else => false,
        };
    }

    pub inline fn isNvptx(arch: Arch) bool {
        return switch (arch) {
            .nvptx, .nvptx64 => true,
            else => false,
        };
    }

    pub fn parseCpuModel(arch: Arch, cpu_name: []const u8) !*const Cpu.Model {
        for (arch.allCpuModels()) |cpu| {
            if (std.mem.eql(u8, cpu_name, cpu.name)) {
                return cpu;
            }
        }
        return error.UnknownCpuModel;
    }

    pub fn endian(arch: Arch) std.builtin.Endian {
        return switch (arch) {
            .avr,
            .arm,
            .aarch64,
            .amdgcn,
            .bpfel,
            .csky,
            .xtensa,
            .hexagon,
            .kalimba,
            .mipsel,
            .mips64el,
            .msp430,
            .nvptx,
            .nvptx64,
            .powerpcle,
            .powerpc64le,
            .riscv32,
            .riscv64,
            .x86,
            .x86_64,
            .wasm32,
            .wasm64,
            .xcore,
            .thumb,
            .ve,
            // GPU bitness is opaque. For now, assume little endian.
            .spirv,
            .spirv32,
            .spirv64,
            .loongarch32,
            .loongarch64,
            .arc,
            .propeller,
            => .little,

            .armeb,
            .aarch64_be,
            .bpfeb,
            .m68k,
            .mips,
            .mips64,
            .powerpc,
            .powerpc64,
            .thumbeb,
            .sparc,
            .sparc64,
            .lanai,
            .s390x,
            => .big,
        };
    }

    /// Returns a name that matches the lib/std/target/* source file name.
    pub fn genericName(arch: Arch) [:0]const u8 {
        return switch (arch) {
            .arm, .armeb, .thumb, .thumbeb => "arm",
            .aarch64, .aarch64_be => "aarch64",
            .bpfel, .bpfeb => "bpf",
            .loongarch32, .loongarch64 => "loongarch",
            .mips, .mipsel, .mips64, .mips64el => "mips",
            .powerpc, .powerpcle, .powerpc64, .powerpc64le => "powerpc",
            .propeller => "propeller",
            .riscv32, .riscv64 => "riscv",
            .sparc, .sparc64 => "sparc",
            .s390x => "s390x",
            .x86, .x86_64 => "x86",
            .nvptx, .nvptx64 => "nvptx",
            .wasm32, .wasm64 => "wasm",
            .spirv, .spirv32, .spirv64 => "spirv",
            else => @tagName(arch),
        };
    }

    /// All CPU features Zig is aware of, sorted lexicographically by name.
    pub fn allFeaturesList(arch: Arch) []const Cpu.Feature {
        return switch (arch) {
            .arm, .armeb, .thumb, .thumbeb => &arm.all_features,
            .aarch64, .aarch64_be => &aarch64.all_features,
            .arc => &arc.all_features,
            .avr => &avr.all_features,
            .bpfel, .bpfeb => &bpf.all_features,
            .csky => &csky.all_features,
            .hexagon => &hexagon.all_features,
            .lanai => &lanai.all_features,
            .loongarch32, .loongarch64 => &loongarch.all_features,
            .m68k => &m68k.all_features,
            .mips, .mipsel, .mips64, .mips64el => &mips.all_features,
            .msp430 => &msp430.all_features,
            .powerpc, .powerpcle, .powerpc64, .powerpc64le => &powerpc.all_features,
            .amdgcn => &amdgcn.all_features,
            .riscv32, .riscv64 => &riscv.all_features,
            .sparc, .sparc64 => &sparc.all_features,
            .spirv, .spirv32, .spirv64 => &spirv.all_features,
            .s390x => &s390x.all_features,
            .x86, .x86_64 => &x86.all_features,
            .xcore => &xcore.all_features,
            .xtensa => &xtensa.all_features,
            .nvptx, .nvptx64 => &nvptx.all_features,
            .ve => &ve.all_features,
            .wasm32, .wasm64 => &wasm.all_features,

            else => &[0]Cpu.Feature{},
        };
    }

    /// All processors Zig is aware of, sorted lexicographically by name.
    pub fn allCpuModels(arch: Arch) []const *const Cpu.Model {
        return switch (arch) {
            .arc => comptime allCpusFromDecls(arc.cpu),
            .arm, .armeb, .thumb, .thumbeb => comptime allCpusFromDecls(arm.cpu),
            .aarch64, .aarch64_be => comptime allCpusFromDecls(aarch64.cpu),
            .avr => comptime allCpusFromDecls(avr.cpu),
            .bpfel, .bpfeb => comptime allCpusFromDecls(bpf.cpu),
            .csky => comptime allCpusFromDecls(csky.cpu),
            .hexagon => comptime allCpusFromDecls(hexagon.cpu),
            .lanai => comptime allCpusFromDecls(lanai.cpu),
            .loongarch32, .loongarch64 => comptime allCpusFromDecls(loongarch.cpu),
            .m68k => comptime allCpusFromDecls(m68k.cpu),
            .mips, .mipsel, .mips64, .mips64el => comptime allCpusFromDecls(mips.cpu),
            .msp430 => comptime allCpusFromDecls(msp430.cpu),
            .powerpc, .powerpcle, .powerpc64, .powerpc64le => comptime allCpusFromDecls(powerpc.cpu),
            .amdgcn => comptime allCpusFromDecls(amdgcn.cpu),
            .riscv32, .riscv64 => comptime allCpusFromDecls(riscv.cpu),
            .sparc, .sparc64 => comptime allCpusFromDecls(sparc.cpu),
            .spirv, .spirv32, .spirv64 => comptime allCpusFromDecls(spirv.cpu),
            .s390x => comptime allCpusFromDecls(s390x.cpu),
            .x86, .x86_64 => comptime allCpusFromDecls(x86.cpu),
            .xcore => comptime allCpusFromDecls(xcore.cpu),
            .xtensa => comptime allCpusFromDecls(xtensa.cpu),
            .nvptx, .nvptx64 => comptime allCpusFromDecls(nvptx.cpu),
            .ve => comptime allCpusFromDecls(ve.cpu),
            .wasm32, .wasm64 => comptime allCpusFromDecls(wasm.cpu),

            else => &[0]*const Model{},
        };
    }

    fn allCpusFromDecls(comptime cpus: type) []const *const Cpu.Model {
        @setEvalBranchQuota(2000);
        const decls = @typeInfo(cpus).@"struct".decls;
        var array: [decls.len]*const Cpu.Model = undefined;
        for (decls, 0..) |decl, i| {
            array[i] = &@field(cpus, decl.name);
        }
        const finalized = array;
        return &finalized;
    }

    /// 0c spim    little-endian MIPS 3000 family
    /// 1c 68000   Motorola MC68000
    /// 2c 68020   Motorola MC68020
    /// 5c arm     little-endian ARM
    /// 6c amd64   AMD64 and compatibles (e.g., Intel EM64T)
    /// 7c arm64   ARM64 (ARMv8)
    /// 8c 386     Intel x86, i486, Pentium, etc.
    /// kc sparc   Sun SPARC
    /// qc power   Power PC
    /// vc mips    big-endian MIPS 3000 family
    pub fn plan9Ext(arch: Cpu.Arch) [:0]const u8 {
        return switch (arch) {
            .arm => ".5",
            .x86_64 => ".6",
            .aarch64 => ".7",
            .x86 => ".8",
            .sparc => ".k",
            .powerpc, .powerpcle => ".q",
            .mips, .mipsel => ".v",
            // ISAs without designated characters get 'X' for lack of a better option.
            else => ".X",
        };
    }

    /// Returns the array of `Arch` to which a specific `std.builtin.CallingConvention` applies.
    /// Asserts that `cc` is not `.auto`, `.@"async"`, `.naked`, or `.@"inline"`.
    pub fn fromCallingConvention(cc: std.builtin.CallingConvention.Tag) []const Arch {
        return switch (cc) {
            .auto,
            .@"async",
            .naked,
            .@"inline",
            => unreachable,

            .x86_64_sysv,
            .x86_64_win,
            .x86_64_regcall_v3_sysv,
            .x86_64_regcall_v4_win,
            .x86_64_vectorcall,
            .x86_64_interrupt,
            => &.{.x86_64},

            .x86_sysv,
            .x86_win,
            .x86_stdcall,
            .x86_fastcall,
            .x86_thiscall,
            .x86_thiscall_mingw,
            .x86_regcall_v3,
            .x86_regcall_v4_win,
            .x86_vectorcall,
            .x86_interrupt,
            => &.{.x86},

            .aarch64_aapcs,
            .aarch64_aapcs_darwin,
            .aarch64_aapcs_win,
            .aarch64_vfabi,
            .aarch64_vfabi_sve,
            => &.{ .aarch64, .aarch64_be },

            .arm_aapcs,
            .arm_aapcs_vfp,
            .arm_interrupt,
            => &.{ .arm, .armeb, .thumb, .thumbeb },

            .mips64_n64,
            .mips64_n32,
            .mips64_interrupt,
            => &.{ .mips64, .mips64el },

            .mips_o32,
            .mips_interrupt,
            => &.{ .mips, .mipsel },

            .riscv64_lp64,
            .riscv64_lp64_v,
            .riscv64_interrupt,
            => &.{.riscv64},

            .riscv32_ilp32,
            .riscv32_ilp32_v,
            .riscv32_interrupt,
            => &.{.riscv32},

            .sparc64_sysv,
            => &.{.sparc64},

            .sparc_sysv,
            => &.{.sparc},

            .powerpc64_elf,
            .powerpc64_elf_altivec,
            .powerpc64_elf_v2,
            => &.{ .powerpc64, .powerpc64le },

            .powerpc_sysv,
            .powerpc_sysv_altivec,
            .powerpc_aix,
            .powerpc_aix_altivec,
            => &.{ .powerpc, .powerpcle },

            .wasm_mvp,
            => &.{ .wasm64, .wasm32 },

            .arc_sysv,
            => &.{.arc},

            .avr_gnu,
            .avr_builtin,
            .avr_signal,
            .avr_interrupt,
            => &.{.avr},

            .bpf_std,
            => &.{ .bpfel, .bpfeb },

            .csky_sysv,
            .csky_interrupt,
            => &.{.csky},

            .hexagon_sysv,
            .hexagon_sysv_hvx,
            => &.{.hexagon},

            .lanai_sysv,
            => &.{.lanai},

            .loongarch64_lp64,
            => &.{.loongarch64},

            .loongarch32_ilp32,
            => &.{.loongarch32},

            .m68k_sysv,
            .m68k_gnu,
            .m68k_rtd,
            .m68k_interrupt,
            => &.{.m68k},

            .msp430_eabi,
            => &.{.msp430},

            .propeller_sysv,
            => &.{.propeller},

            .s390x_sysv,
            .s390x_sysv_vx,
            => &.{.s390x},

            .ve_sysv,
            => &.{.ve},

            .xcore_xs1,
            .xcore_xs2,
            => &.{.xcore},

            .xtensa_call0,
            .xtensa_windowed,
            => &.{.xtensa},

            .amdgcn_device,
            .amdgcn_kernel,
            .amdgcn_cs,
            => &.{.amdgcn},

            .nvptx_device,
            .nvptx_kernel,
            => &.{ .nvptx, .nvptx64 },

            .spirv_device,
            .spirv_kernel,
            .spirv_fragment,
            .spirv_vertex,
            => &.{ .spirv, .spirv32, .spirv64 },
        };
    }
}  