Source
pub const cpu = struct {
pub const @"440": CpuModel = .{
.name = "440",
.llvm_name = "440",
.features = featureSet(&[_]Feature{
.fres,
.frsqrte,
.isel,
.msync,
}),
};
pub const @"450": CpuModel = .{
.name = "450",
.llvm_name = "450",
.features = featureSet(&[_]Feature{
.fres,
.frsqrte,
.isel,
.msync,
}),
};
pub const @"601": CpuModel = .{
.name = "601",
.llvm_name = "601",
.features = featureSet(&[_]Feature{
.fpu,
}),
};
pub const @"602": CpuModel = .{
.name = "602",
.llvm_name = "602",
.features = featureSet(&[_]Feature{
.fpu,
}),
};
pub const @"603": CpuModel = .{
.name = "603",
.llvm_name = "603",
.features = featureSet(&[_]Feature{
.fres,
.frsqrte,
}),
};
pub const @"603e": CpuModel = .{
.name = "603e",
.llvm_name = "603e",
.features = featureSet(&[_]Feature{
.fres,
.frsqrte,
}),
};
pub const @"603ev": CpuModel = .{
.name = "603ev",
.llvm_name = "603ev",
.features = featureSet(&[_]Feature{
.fres,
.frsqrte,
}),
};
pub const @"604": CpuModel = .{
.name = "604",
.llvm_name = "604",
.features = featureSet(&[_]Feature{
.fres,
.frsqrte,
}),
};
pub const @"604e": CpuModel = .{
.name = "604e",
.llvm_name = "604e",
.features = featureSet(&[_]Feature{
.fres,
.frsqrte,
}),
};
pub const @"620": CpuModel = .{
.name = "620",
.llvm_name = "620",
.features = featureSet(&[_]Feature{
.fres,
.frsqrte,
}),
};
pub const @"7400": CpuModel = .{
.name = "7400",
.llvm_name = "7400",
.features = featureSet(&[_]Feature{
.altivec,
.fres,
.frsqrte,
}),
};
pub const @"7450": CpuModel = .{
.name = "7450",
.llvm_name = "7450",
.features = featureSet(&[_]Feature{
.altivec,
.fres,
.frsqrte,
}),
};
pub const @"750": CpuModel = .{
.name = "750",
.llvm_name = "750",
.features = featureSet(&[_]Feature{
.fres,
.frsqrte,
}),
};
pub const @"970": CpuModel = .{
.name = "970",
.llvm_name = "970",
.features = featureSet(&[_]Feature{
.@"64bit",
.altivec,
.fres,
.frsqrte,
.fsqrt,
.mfocrf,
.stfiwx,
}),
};
pub const a2: CpuModel = .{
.name = "a2",
.llvm_name = "a2",
.features = featureSet(&[_]Feature{
.@"64bit",
.booke,
.cmpb,
.fcpsgn,
.fpcvt,
.fprnd,
.fre,
.fres,
.frsqrte,
.frsqrtes,
.fsqrt,
.isa_v206_instructions,
.isel,
.ldbrx,
.lfiwax,
.mfocrf,
.recipprec,
.slow_popcntd,
.stfiwx,
}),
};
pub const e500: CpuModel = .{
.name = "e500",
.llvm_name = "e500",
.features = featureSet(&[_]Feature{
.isel,
.msync,
.spe,
}),
};
pub const e500mc: CpuModel = .{
.name = "e500mc",
.llvm_name = "e500mc",
.features = featureSet(&[_]Feature{
.booke,
.isel,
.stfiwx,
}),
};
pub const e5500: CpuModel = .{
.name = "e5500",
.llvm_name = "e5500",
.features = featureSet(&[_]Feature{
.@"64bit",
.booke,
.isel,
.mfocrf,
.stfiwx,
}),
};
pub const future: CpuModel = .{
.name = "future",
.llvm_name = "future",
.features = featureSet(&[_]Feature{
.@"64bit",
.allow_unaligned_fp_access,
.bpermd,
.cmpb,
.crbits,
.crypto,
.direct_move,
.extdiv,
.fast_MFLR,
.fcpsgn,
.fpcvt,
.fprnd,
.fre,
.fres,
.frsqrte,
.frsqrtes,
.fsqrt,
.fuse_add_logical,
.fuse_arith_add,
.fuse_logical,
.fuse_logical_add,
.fuse_sha3,
.fuse_store,
.icbt,
.isa_future_instructions,
.isa_v206_instructions,
.isel,
.ldbrx,
.lfiwax,
.mfocrf,
.mma,
.partword_atomics,
.pcrelative_memops,
.popcntd,
.power10_vector,
.ppc_postra_sched,
.ppc_prera_sched,
.predictable_select_expensive,
.quadword_atomics,
.recipprec,
.stfiwx,
.two_const_nr,
}),
};
pub const g3: CpuModel = .{
.name = "g3",
.llvm_name = "g3",
.features = featureSet(&[_]Feature{
.fres,
.frsqrte,
}),
};
pub const g4: CpuModel = .{
.name = "g4",
.llvm_name = "g4",
.features = featureSet(&[_]Feature{
.altivec,
.fres,
.frsqrte,
}),
};
pub const @"g4+": CpuModel = .{
.name = "g4+",
.llvm_name = "g4+",
.features = featureSet(&[_]Feature{
.altivec,
.fres,
.frsqrte,
}),
};
pub const g5: CpuModel = .{
.name = "g5",
.llvm_name = "g5",
.features = featureSet(&[_]Feature{
.@"64bit",
.altivec,
.fres,
.frsqrte,
.fsqrt,
.mfocrf,
.stfiwx,
}),
};
pub const generic: CpuModel = .{
.name = "generic",
.llvm_name = "generic",
.features = featureSet(&[_]Feature{
.hard_float,
}),
};
pub const ppc: CpuModel = .{
.name = "ppc",
.llvm_name = "ppc",
.features = featureSet(&[_]Feature{
.hard_float,
}),
};
pub const ppc64: CpuModel = .{
.name = "ppc64",
.llvm_name = "ppc64",
.features = featureSet(&[_]Feature{
.@"64bit",
.altivec,
.fres,
.frsqrte,
.fsqrt,
.mfocrf,
.stfiwx,
}),
};
pub const ppc64le: CpuModel = .{
.name = "ppc64le",
.llvm_name = "ppc64le",
.features = featureSet(&[_]Feature{
.@"64bit",
.allow_unaligned_fp_access,
.bpermd,
.cmpb,
.crbits,
.crypto,
.direct_move,
.extdiv,
.fcpsgn,
.fpcvt,
.fprnd,
.fre,
.fres,
.frsqrte,
.frsqrtes,
.fsqrt,
.fuse_addi_load,
.fuse_addis_load,
.htm,
.icbt,
.isa_v206_instructions,
.isa_v207_instructions,
.isel,
.ldbrx,
.lfiwax,
.mfocrf,
.partword_atomics,
.popcntd,
.power8_vector,
.predictable_select_expensive,
.quadword_atomics,
.recipprec,
.stfiwx,
.two_const_nr,
}),
};
pub const pwr10: CpuModel = .{
.name = "pwr10",
.llvm_name = "pwr10",
.features = featureSet(&[_]Feature{
.@"64bit",
.allow_unaligned_fp_access,
.bpermd,
.cmpb,
.crbits,
.crypto,
.direct_move,
.extdiv,
.fast_MFLR,
.fcpsgn,
.fpcvt,
.fprnd,
.fre,
.fres,
.frsqrte,
.frsqrtes,
.fsqrt,
.fuse_add_logical,
.fuse_arith_add,
.fuse_logical,
.fuse_logical_add,
.fuse_sha3,
.fuse_store,
.icbt,
.isa_v206_instructions,
.isel,
.ldbrx,
.lfiwax,
.mfocrf,
.mma,
.partword_atomics,
.pcrelative_memops,
.popcntd,
.power10_vector,
.ppc_postra_sched,
.ppc_prera_sched,
.predictable_select_expensive,
.quadword_atomics,
.recipprec,
.stfiwx,
.two_const_nr,
}),
};
pub const pwr11: CpuModel = .{
.name = "pwr11",
.llvm_name = "pwr11",
.features = featureSet(&[_]Feature{
.@"64bit",
.allow_unaligned_fp_access,
.bpermd,
.cmpb,
.crbits,
.crypto,
.direct_move,
.extdiv,
.fast_MFLR,
.fcpsgn,
.fpcvt,
.fprnd,
.fre,
.fres,
.frsqrte,
.frsqrtes,
.fsqrt,
.fuse_add_logical,
.fuse_arith_add,
.fuse_logical,
.fuse_logical_add,
.fuse_sha3,
.fuse_store,
.icbt,
.isa_v206_instructions,
.isel,
.ldbrx,
.lfiwax,
.mfocrf,
.mma,
.partword_atomics,
.pcrelative_memops,
.popcntd,
.power10_vector,
.ppc_postra_sched,
.ppc_prera_sched,
.predictable_select_expensive,
.quadword_atomics,
.recipprec,
.stfiwx,
.two_const_nr,
}),
};
pub const pwr3: CpuModel = .{
.name = "pwr3",
.llvm_name = "pwr3",
.features = featureSet(&[_]Feature{
.@"64bit",
.altivec,
.fres,
.frsqrte,
.mfocrf,
.stfiwx,
}),
};
pub const pwr4: CpuModel = .{
.name = "pwr4",
.llvm_name = "pwr4",
.features = featureSet(&[_]Feature{
.@"64bit",
.altivec,
.fres,
.frsqrte,
.fsqrt,
.mfocrf,
.stfiwx,
}),
};
pub const pwr5: CpuModel = .{
.name = "pwr5",
.llvm_name = "pwr5",
.features = featureSet(&[_]Feature{
.@"64bit",
.altivec,
.fre,
.fres,
.frsqrte,
.frsqrtes,
.fsqrt,
.mfocrf,
.stfiwx,
}),
};
pub const pwr5x: CpuModel = .{
.name = "pwr5x",
.llvm_name = "pwr5x",
.features = featureSet(&[_]Feature{
.@"64bit",
.altivec,
.fprnd,
.fre,
.fres,
.frsqrte,
.frsqrtes,
.fsqrt,
.mfocrf,
.stfiwx,
}),
};
pub const pwr6: CpuModel = .{
.name = "pwr6",
.llvm_name = "pwr6",
.features = featureSet(&[_]Feature{
.@"64bit",
.altivec,
.cmpb,
.fcpsgn,
.fprnd,
.fre,
.fres,
.frsqrte,
.frsqrtes,
.fsqrt,
.lfiwax,
.mfocrf,
.recipprec,
.stfiwx,
}),
};
pub const pwr6x: CpuModel = .{
.name = "pwr6x",
.llvm_name = "pwr6x",
.features = featureSet(&[_]Feature{
.@"64bit",
.altivec,
.cmpb,
.fcpsgn,
.fprnd,
.fre,
.fres,
.frsqrte,
.frsqrtes,
.fsqrt,
.lfiwax,
.mfocrf,
.recipprec,
.stfiwx,
}),
};
pub const pwr7: CpuModel = .{
.name = "pwr7",
.llvm_name = "pwr7",
.features = featureSet(&[_]Feature{
.@"64bit",
.allow_unaligned_fp_access,
.bpermd,
.cmpb,
.extdiv,
.fcpsgn,
.fpcvt,
.fprnd,
.fre,
.fres,
.frsqrte,
.frsqrtes,
.fsqrt,
.isa_v206_instructions,
.isel,
.ldbrx,
.lfiwax,
.mfocrf,
.popcntd,
.recipprec,
.stfiwx,
.two_const_nr,
.vsx,
}),
};
pub const pwr8: CpuModel = .{
.name = "pwr8",
.llvm_name = "pwr8",
.features = featureSet(&[_]Feature{
.@"64bit",
.allow_unaligned_fp_access,
.bpermd,
.cmpb,
.crbits,
.crypto,
.direct_move,
.extdiv,
.fcpsgn,
.fpcvt,
.fprnd,
.fre,
.fres,
.frsqrte,
.frsqrtes,
.fsqrt,
.fuse_addi_load,
.fuse_addis_load,
.htm,
.icbt,
.isa_v206_instructions,
.isa_v207_instructions,
.isel,
.ldbrx,
.lfiwax,
.mfocrf,
.partword_atomics,
.popcntd,
.power8_vector,
.predictable_select_expensive,
.quadword_atomics,
.recipprec,
.stfiwx,
.two_const_nr,
}),
};
pub const pwr9: CpuModel = .{
.name = "pwr9",
.llvm_name = "pwr9",
.features = featureSet(&[_]Feature{
.@"64bit",
.allow_unaligned_fp_access,
.bpermd,
.cmpb,
.crbits,
.crypto,
.direct_move,
.extdiv,
.fcpsgn,
.fpcvt,
.fprnd,
.fre,
.fres,
.frsqrte,
.frsqrtes,
.fsqrt,
.htm,
.icbt,
.isa_v206_instructions,
.isel,
.ldbrx,
.lfiwax,
.mfocrf,
.partword_atomics,
.popcntd,
.power9_vector,
.ppc_postra_sched,
.ppc_prera_sched,
.predictable_select_expensive,
.quadword_atomics,
.recipprec,
.stfiwx,
.two_const_nr,
.vectors_use_two_units,
}),
};
}